The present invention relates to an SOI-MOS field effect transistor and a method of forming the same.
One of conventional SOI-MOS field effect transistors will be described with reference to FIG. 3. A buried oxide film 2 is provided over a silicon substrate 1. Field oxide films 4 are selectively formed on the buried oxide film 2. A silicon-on-insulator layer 3 made of silicon is formed over the buried oxide film 2 wherein the silicon-on-insulator layer 3 is defined by the field oxide films 4. The silicon-on-insulator layer 3 has n-type source/drain regions 10 and 9 and a p-type body portion 5 between the n-type source/drain regions 10 and 9. A gate oxide film 6 is provided which extends over the p-type body portion 5 and inside portions of the n-type source/drain regions 10 and 9 in the vicinity of the body portion 5. A gate electrode 7 is provided on the gate oxide film 6 so that the gate electrode 7 is positioned over the body portion S. Side wall oxide films 8 are also provided on side walls of the gate electrode 7 and over the gate oxide film 6. An inter-layer insulator 11 is further provided over the field oxide films 4, the silicon-on-insulator layer 3 and the gate electrode 7 as well as over the side wall oxide films 8. Contact holes 12 are formed in the inter-layer insulator 11 so that the contact holes 12 are positioned over the source/drain regions 10 and 9. Contact layers are formed in the contact holes 12 so that the contact layers are in contact with the source/drain regions 10 and 9. Metal interconnections 13 are provided which are connected to the contact layers so that the metal interconnections 13 are electrically connected to the source/drain regions 10 and 9.
FIG. 1 is a graph illustrative of sub-threshold characteristics (Id-Vg characteristics) or current-voltage characteristics of the above first conventional SOI-MOS field effect transistor when applied with drain voltages of 1.5 V and 0.05 V. If the drain voltage of 0.05 V is applied to the drain electrode of the above first conventional SOI-MOS field effect transistor, then the sub-threshold characteristic is normal and free of any kink effect. If, however, the drain voltage of 1.5 V is applied to the drain electrode of the above first conventional SOI-MOS field effect transistor, then the sub-threshold characteristic exhibits a kink effect. It was known that such kink effect may appear when the drain voltage is not less than about 0.8 V. The following descriptions will focus on the mechanism of the kink effect.
When the above n-channel MOS field effect transistor is in the ON-state, electrons move from the n-type source region 10 through an inversion layer in the p-type body portion 5 to the n-type drain region 9. When electrons are injected into the drain region 9 from the inversion layer of the body portion 5, an impact ionization is caused at a drain edge portion of the inversion layer adjacent to the drain region 9. The impact ionization generates electron-hole pairs. Electrons generated by the impact ionization move into the drain region and are then absorbed therein, whilst the holes generated by the impact ionization are accumulated on an interface of the p-type body portion 5 to the n-type source region 10, wherein the p-type body portion 5 is electrically floated. The accumulation of the holes on the interface of the p-type body portion 5 to the n-type source region 10 rises a potential of the p-type body portion 5. A parasitic bipolar transistor is caused. The drain region 9 virtually corresponds to the collector region. The hole accumulated interface of the body portion to the source region serve as a base region. The source region 10 serves as an emitter. When a potential difference between the hole accumulated interface of the body portion to the source region and the source region 10 is increased beyond a threshold voltage of the parasitic bipolar transistor, then the parasitic bipolar transistor turns ON. As a result, the holes accumulated on the interface of the body portion 5 to the source region 10 are injected into the source region 10 at a current lb. The injection current of the holes from the body portion 5 to the source region 10 causes an additional current from the source region 10 to the drain region 9 through the body portion 5 is caused, wherein the additional current is defined by the product of the above current value Ib and a current amplification factor of the parasitic bipolar transistor. Such the additional current caused by the parasitic bipolar transistor causes the kink effect as well illustrated in FIG. 1. This phenomenon is so called as a parasitic bipolar effect. In order to avoid this parasitic bipolar effect, it is effective to allow a leakage of current between the body portion and the source region so that the holes accumulated on the interface of the body portion to the source region 5 are allowed to flow into the source region 10, thereby to suppress the increase in potential of the body portion. Alternatively, it is also effective to decrease the current amplification factor of the parasitic bipolar transistor so as to decrease the additional current whereby the kink effect is suppressed.
In the Japanese laid-open patent publication No. 2-291175, there is disclosed a second conventional SOI-MOS field effect transistor, descriptions of which will hereinafter be made with reference to FIG. 4. A buried oxide film 2 is provided over a silicon substrate 1. Field oxide films 4 are selectively formed on the buried oxide film 2. A silicon-on-insulator layer 3 made of silicon is formed over the buried oxide film 2 wherein the silicon-on-insulator layer 3 is defined by the field oxide films 4. The silicon-on-insulator layer 3 has n-type source/drain regions 10 and 9 and a p-type body portion 5 between the n-type source/drain regions 10 and 9. A gate oxide film 6 is provided which extends over the p-type body portion 5 and inside portions of the n-type source/drain regions 10 and 9 in the vicinity of the body portion 5. A gate electrode 7 is provided on the gate oxide film 6 so that the gate electrode 7 is positioned over the body portion 5. Side wall oxide films 8 are also provided on side walls of the gate electrode 7 and over the gate oxide film 6. A metal layer 15 is further provided which extends over the gate insulation film in the source side and over the source region 10 except in the vicinity of the body portion 5. An inter-layer insulator 11 is further provided over the field oxide films 4, the metal layer 15, the silicon-on-insulator layer 3 and the gate electrode 7 as well as over the side wall oxide films 8. Contact holes 12 are formed in the inter-layer insulator 11 so that the contact holes 12 are positioned over the metal layer 15 over the source region 10 and over the drain region 9. Contact layers are formed in the contact holes 12 so that the contact layers are in contact with the metal layer 15 over the source region 10 and the drain region 9. Metal interconnections 13 are provided which are connected to the contact layers so that the metal interconnections 13 are electrically connected to the source/drain regions 10 and 9.
The metal layer 15 has a lower resistivity than that of the source region 10. The provision of the metal layer 15 allows a leakage of current of holes or promotes that holes accumulated on the interface of the body portion 5 to the source region 10 are injected to the metal layer 15. Such leakage of the holes from the body portion to the source region results in a potential drop of the body portion. This prevents the increase in potential of the body portion. The suppression of the increase in potential of the body portion prevents the increase in potential difference between the body portion and the source region beyond the threshold voltage. This prevents the parasitic bipolar transistor from turning ON whereby no parasitic bipolar effect is caused.
Also, a distance between the metal layer 15 and the body portion 5 of the second conventional SOI-MOS field effect transistor shown in FIG. 4 is shorter than a distance between the contact layer and the body portion of the first conventional SOI-MOS field effect transistor shown in FIG. 3. The shortening of the distance between the metal layer and the body portion means shortening a width of the emitter of the parasitic bipolar transistor. It was known that a life-time of the holes injected from the interface into the source region until those recombination with electrons depends upon the distance between the metal layer and the body portion. If the distance between the metal layer and the body portion is shortened, then the life-time of the holes until the recombination is also shortened. If, however, the distance between the metal layer and the body portion is extended, then the life-time of the holes until the recombination is also extended. The current amplification factor of the parasitic bipolar transistor is defined by the life-time of the holes injected from the interface into the source region until those recombination with electrons. If the life-time of the holes is shortened, then the current amplification factor of the parasitic bipolar transistor is also dropped. If, however, the life-time of the holes is extended, then the current amplification factor of the parasitic bipolar transistor is also risen. The provision of the metal layer 15 shortens the distance between the metal layer 15 and the body portion 5. The shortening of the distance between the metal layer 15 and the body portion 5 results in shortening of the life-time of the holes injected from the interface into the source region until those recombination with electrons. The shortening of the life-time of the holes drops the current amplification factor of the parasitic bipolar transistor.
However, the above second conventional SOI-MOS field effect transistor has no metal layer over the drain region. This results in an increased resistance of the drain region 9. The increase in resistance of the drain region 9 of the SOI-MOS field effect transistor results in deterioration of characteristics of the SOI-MOS field effect transistor.
For scaling down the SOI-MOS field effect transistor, it is essential to form shallow source and drain regions. This means it essential to reduce the thickness of the silicon-on-insulator layer over the buried oxide film over the silicon substrate. The reduction in thickness of the silicon-on-insulator layer causes the increase in source-drain parasitic resistance of the SOI-MOS field effect transistor.
In order to settle the above problems, it was proposed to provide metal layers over the source/drain regions of the SOI-MOS field effect transistor, which is disclosed in Proceedings 1995 IEEE International SOI Conference, pp. 28-29, 1995 Sato et al. "Characteristics of 1/4-mm Gate Ultra-thin Film MOSFETs/SIMOX With Tungsten-Deposited Low-Resistance Source/Drain". It was also proposed to form silicide layers over the source/drain regions of the SOI-MOS field effect transistor, which is disclosed in Proceedings 1996 IEEE International SOI Conference, pp. 78-79, 1996, Deng et al. "Deep Salicidation Using Nickel For Suppressing The Floating Body Effect In Partially Depleted SOI-MOSFET".
The above third conventional SOI-MOS field effect transistor will hereinafter be described with reference to FIG. 5. A buried oxide film 2 is provided over a silicon substrate 1. Field oxide films 4 are selectively formed on the buried oxide film 2. A silicon-on-insulator layer 3 made of silicon is formed over the buried oxide film 2 wherein the silicon-on-insulator layer 3 is defined by the field oxide films 4. The silicon-on-insulator layer 3 has n-type source/drain regions 10 and 9 and a p-type body portion 5 between the n-type source/drain regions 10 and 9. A gate oxide film 6 is provided which extends over the p-type body portion 5 and inside portions of the n-type source/drain regions 10 and 9 in the vicinity of the body portion 5. A gate electrode 7 is provided on the gate oxide film 6 so that the gate electrode 7 is positioned over the body portion 5. The gate electrode 7 has an upper region which comprises a silicide layer. Side wall oxide films 8 are also provided on side walls of the gate electrode 7 and over the gate oxide film 6. Silicide layers 16 are further formed in upper regions of the source and drain regions 10 and 9 except in the vicinity of the body portion 5 by self-alignment technique. The silicide layers 16 may be considered to be salicide layers. An inter-layer insulator 11 is further provided over the field oxide films 4, the silicide layers 16 and the gate electrode 7 as well as over the side wall oxide films 8. Contact holes 12 are formed in the inter-layer insulator 11 so that the contact holes 12 are positioned over the metal layer 15 over the source region 10 and over the drain region 9. Contact layers are formed in the contact holes 12 so that the contact layers are in contact with the metal layer 15 over the source region 10 and the drain region 9. Metal interconnections 13 are provided which are connected to the contact layers so that the metal interconnections 13 are electrically connected to the source/drain regions 10 and 9.
The silicidation of the source and drain regions results in not only a reduction of the parasitic resistance of the source and drain regions but also a suppression of the parasitic bipolar transistor.
The provision of the silicide layers in the upper regions of the source and drain regions shortens the distance between the silicide layers 16 and the body portion 5. The life-time of the holes injected from the interface of the body portion 5 into the source region 10 until the recombination of the injected holes with electrons is defined by the distance between the silicide layers 16 and the body portion 5. For this reason, the shortening of the distance between the silicide layers 16 and the body portion 5 results in shortening of the life-time of the holes injected from the interface of the body portion 5 into the source region 10 until the recombination of the injected holes with electrons. The current amplification factor of the parasitic bipolar transistor is defined by the lifetime of the holes injected from the interface of the body portion 5 into the source region 10 until the recombination of the injected holes with electrons. Therefore, the shortening of the life-time of the holes injected from the interface of the body portion 5 into the source region 10 until the recombination of the injected holes with electrons results in a reduction in the current amplification factor of the parasitic bipolar transistor. The reduction in current amplification factor of the parasitic bipolar transistor suppresses the parasitic bipolar effect of the SOI-MOS field effect transistor.
In the above third conventional SOI-MOS field effect transistor, however, in order to reduce the parasitic resistances of the shallow source/drain regions, the silicide layers or salicide layers are formed in upper regions of the shallow source/drain regions.
Consequently, in order to reduce the parasitic resistances of the shallow source/drain regions, the silicide layers or salicide layers and also suppress the parasitic bipolar effect of the SOI-MOS field effect transistor, it is effective to form metal layers or silicide layers selectively in upper regions of the source/drain regions of the SOI-MOS field effect transistor, so that the life-time of the holes injected from the interface of the body portion 5 into the source region 10 until the recombination of the injected holes with electrons is shortened, whereby the current amplification factor of the parasitic bipolar transistor is suppressed and the parasitic bipolar effect of the SOI-MOS field effect transistor is thus suppressed.
The provisions of the metal layers or the silicide layers in the upper regions of the source and drain regions renders the SOI-MOS field effect transistor free from the kink effect as illustrated in FIG. 1. Notwithstanding, the drain region and the metal or silicide layer in the drain region are applied with the drain voltage which is usually a high voltage. Further, the distance between the body portion 5 and the silicide or metal layer of the drain region is shortened. Both the provision of the silicide layer or the metal layer in the upper region of the drain region and the application of the high voltage to the drain region results in allowance of a large leakage of current between the drain region 9 and the body portion 5. This large leakage of current between the drain region 9 and the body portion 5 causes a serious problem with a large OFF current of the SOI-MOS field effect transistor under zero gate voltage application, resulting in an increase in power consumption of the SOI-MOS field effect transistor. If, however, no metal layer nor silicide layer is provided in the drain region to settle the problem with the large leakage of current between the drain region and the body portion, then the above described other problems with increase in resistance of the drain as well as with the increase in parasitic resistance by the shallow p-n junctions of the source and drain regions or the difficulty in thickness of the silicon-on-insulator layer.
In the above circumstances, it had been required to develop a novel SOI-MOS field effect transistor free from all of the above problems.